1. Field of the Invention
The present invention relates to a level shift circuit, and more particularly, to a Level shift circuit without high voltage stress of transistors and operating at low voltages.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a circuitry of a level shift circuit 10 according to the prior art. The level shift circuit 10 includes two PMOS transistors P1 and P2, and two NMOS transistors N1 and N2. A gate of the transistor N2 is electrically connected to a voltage source Vdd. A source of the transistor P2 and a source of the transistor P1 are electrically connected to a high voltage terminal Vn. An input voltage Vin ranges between a high level voltage (the voltage Vdd) and a low level voltage (a ground voltage).
Assumed the high voltage Vn is 10 volts and the voltage Vdd is 3.3 volts, and the breakdown voltage level of each of the transistors P1, P2, N1 and N2 is 10 volts. When the input voltage Vin is at the high level voltage, the transistor N1 is turned on and the transistor N2 is turned off. A voltage level at the node A1 approaches to the ground voltage and the transistor P2 is turned on. A voltage level at a node A2 approaches to the high voltage Vn and the transistor P1 is turned off. Thus, the output voltage Vout of the level shift circuit 10 approaches to 0 volts. Although the transistors P2 and N1 are turned on, a reverse voltage across the drains and the gates of both the transistors P2 approaches to 10 volts, which results in a number of breakdown currents appearing in a corresponding oxide layer, destroying the level shift circuit 10.
When the input voltage Vin is at the low level voltage, the transistor N1 is turned off and the transistor N2 is turned on. A voltage level at the node A2 approaches to the low level voltage and the transistor P1 is turned on. A voltage level at the node A1 approaches to the high voltage Vn and the transistor P2 is turned off. Thus, the output voltage Vout of the level shift circuit 10 approaches to 10 volts. Although the transistors N2 and P1 are turned on, a reverse voltage across the drains and the gates of the transistors P1 still approaches to 10 volts, which results in a number of breakdown currents appearing in a corresponding oxide layer destroying the level shift circuit 10. To prevent the transistors P1 and P2 from a breakdown, the level shift circuit 10 has to control the voltage level of the high voltage terminal Vn to guarantee that the transistors P1 and P2 function normally.
U.S. Pat. No. 6,580,307 provides a level shift circuit without junction breakdown of transistors. Please refer to FIG. 2. The circuit 80 includes a plurality of PMOS transistors 86, 88, 90, and 92, and a plurality of NMOS transistors 82, 84, and 94. If a voltage level of the source (the node C) is greater than a sum of a threshold voltage Vt of the transistor 86 and a voltage level of a gate of the transistor 86, the transistor 86 actuates and then the transistor 90 also actuates, which makes a voltage level at a node D approach 10 volts (Vn). The actuated transistor 86 gradually reduces the voltage level at the node C until it is smaller than the sum of the threshold voltage Vt of the transistor 86 and the voltage level of the gate of the transistor 86. Because a voltage level difference between the drain and the gate exceeds 6.6 volts, the transistor 90 will not break down. Likewise, the transistor 88 will not break down either. Because a voltage level at the node D approaches 10 volts, the transistor 92 will actuate and then a voltage level at a node A approaches 10 volts.
On the contrary, if the input voltage Vin is zero, the transistor 82 does not actuate and the transistor 94 actuates, which makes the voltage level at the node A approach zero volts. Because the gate of the transistors 86, 92 are connected to the reference voltage Vk (3.3 volts), both transistors 86, 92 do not actuate, which makes the voltage level at the node A and the voltage level at the node D different. When a voltage level of a source (the node D) of the transistor 92 is greater than a sum of a threshold voltage Vt of the transistor 92 and a voltage level of the gate of the transistor 92, the transistor 92 actuates. The voltage level at the node D approaches to the sum of the threshold voltage of the transistor 92 and the voltage level Vk of the gate of the transistor 92. The actuated transistor 92 actuates the transistor 88 and makes the voltage level at the node C approach 10 volts.
The level shift circuit 80 uses the reference voltage Vk to control actuations of the transistors 86, 92, which is capable of preventing the gate s of the transistors 88, 90 from breaking down. However, when the level shift circuit 80 operates at low voltages, the voltage terminal Vn has to overcome two threshold voltages.